Try to further simplify. Hide Plot ». Sign In. Sign in with Office Sign in with Facebook. Forgot Password Please enter your email address. An email notification with password reset instructions will be sent to you. Send Reset Link. We've sent the email to: [email protected]. Join million happy users! Sign Up free of charge:. Join with Office If this reduced bandwidth is lower than the closed-loop bandwidth of the diff-amp, the circuit will be stable. This bandwidth-limiting technique can also be employed with a gain of two by making R G an open circuit.
His design work currently focuses on fully differential amplifiers with either fixed, variable, or programmable gains. Sandro holds B. He joined Analog Devices in August Moshe Gerstenhaber is a division fellow at Analog Devices. He began his career at ADI in and has held various senior positions over the years in manufacturing, product engineering, and product design.
Moshe is currently the design manager of the Integrated Amplifier Products Group. A circuit with a balanced architecture is much less sensitive to crosstalk compared to a single ended equivalent. A further advantage of a balanced architecture is that signal inversion is simply achieved by cross-coupling two signals. A general problem is the making of two balanced signals from one single ended signal having low distortion and good balancing at high frequencies.
Commonly a simple differential pair structure is used having one input coupled to the single ended signal and the other input coupled to a fixed DC voltage. A problem in the differential pair is that the inverting and non-inverting output signals of the differential pair have unequal delays in respect of the input signal due to the capacitance present at the common node of the differential pair.
This results in output signals having a phase difference unequal to degrees. It is an object of the invention to provide an accurate single-to-differential converter with low distortion and good balancing over a high frequency range. According to the invention a single-to-differential converter for generating two balanced output signals from one single ended input signal is provided, which is characterized in that the single-to-differential converter comprises:.
In this single-to-differential converter the main current paths of the first and third transistors are operationally connected in series. A voltage increase at the control electrode of the first transistor causes for example a current increase in the series connection. The current increase causes a voltage increase across the diode-connected third transistor, so that the voltage increase at the control electrode of the first transistor is copied in the diode-connected third transistor.
The main current paths of the second and fourth transistors are series connected too. However, the control electrode of the second transistor is grounded for signal changes and its first main electrode receives the input voltage. This arrangement results in a current decrease in the series connected second and fourth transistors in response to the voltage increase at the first main electrode of the second transistor.
The current decrease causes a voltage decrease across the diode-connected fourth transistor which is equal to the voltage increase at the first main electrode of the second transistor. Since the control electrode of the first transistor and the first main electrode of the second transistor are both coupled to the same input terminal, a voltage change at the input terminal will cause equal, but opposite voltage changes at the first and second output terminals, which are connected to the diode-connected third and fourth transistors.
The delay-match in the signal transfer from the input terminal to the first and second output terminals is disturbed only by the parasitic capacitance between the control electrode and the second main electrode of the first transistor. This capacitance causes a zero in the right half-plane of the transfer function from the input terminal to the first output terminal and gives rise to excess phase shift.
Since this zero is located at very high frequencies the phase error can be kept small in the operating frequency range. A first embodiment of the single-to-differential converter is characterized in that the single-to-differential converter further comprises a further supply voltage terminal for receiving a further supply voltage, the first main electrode of the third transistor being coupled to the second main electrode of the first transistor, the second main electrode and control electrode of the third transistor being coupled to the further supply voltage terminal, the first main electrode of the fourth transistor being coupled to the second main electrode of the second transistor and the second main electrode and control electrode of the fourth transistor being coupled to the further supply voltage terminal.
The series arrangement of the first and the third transistors and the series arrangement of the second and the fourth transistors are connected between the first mentioned supply voltage terminal and the further supply voltage terminal. This embodiment needs a minimum number of transistors. A second embodiment of the single-to-differential converter is characterized in that the single-to-differential converter further comprises:. In this embodiment the currents from the first and second transistors are folded back to the first mentioned supply voltage by means of the first and the second current mirrors.
The advantage is the possibility of a lower supply voltage. Furthermore the common-mode level of the output signals is closer to the signal level of the input signal. The input impedance at the input terminal is rather low, because the second transistor is driven at its first main electrode. To increase the input impedance further embodiments of the single-to-differential converter are characterized in that the single-to-differential converter further comprises a fifth transistor having a control electrode coupled to the input terminal, a first main electrode coupled to the supply voltage terminal and a second main electrode coupled to the control electrode of the first transistor.
The fifth transistor in combination with the second transistor operates as a buffer amplifier and provides a high input impedance at the input terminal. To provide the possibility of a current input signal, still further embodiments of the single-to-differential converter may be characterized in that the second main electrode of the fifth transistor is connected to the control electrode of the fifth transistor.
The fifth transistor is now diode-connected and converts the input current to an input voltage. These and further aspects of the invention will be described in further detail with reference to the accompanying drawings, in which:.
In these figures like reference symbols are employed to represent the same item. The circuit employs NMOS transistors having a first main electrode or source, a second main electrode or drain and a control electrode or gate. The source of a first transistor M1 is connected to a supply voltage terminal 1 which in turn is connected to signal ground.
The drain of transistor M1 is coupled via the main current path of a third transistor M3 to a further supply voltage terminal 2 to which a supply voltage Vdd can be connected which is positive with respect to ground.
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